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High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
GENERAL DESCRIPTION
The WS6264 is a high performance, high speed and super low power CMOS Static Random Access Memory organized as 8,192 words by 8bits and operates from a single 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 70ns in 5.0V operation. Easy memory expansion is provided by using two chip enable inputs (/CE1, CE2) and active LOW output enable (/OE). The WS6264 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The WS6264 is available in JEDEC standard 28-pin SOP(300 mil) and PDIP (600 mil) packages.
FEATURES
Operation voltage : 4.5 ~ 5.5V Ultra low power consumption: Operating current 1mA@1MHz & CMOS standby current 1.0uA (Typ.) in Vcc=5.0V High speed access time: 70ns. Automatic power down when chip is deselected. Three state outputs and TTL compatible. Data retention supply voltage as low as 2.0V. Easy expansion with /CE1, CE2 and /OE options.
PRODUCT FAMILY
Product Family WS6264LLFP WS6264LLP WS6264LLFPI WS6264LLPI 0~70oC 4.5~5.5V 70 1.0uA Operating Temp. Vcc Range Speed (ns) Standby Current (Typ.)
ICCSB1
Package Type 28 SOP 28 PDIP 28 SOP 28 PDIP
o -40~85 C
70
1.0uA
Rev. 1.0
1
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
PIN CONFIGURATIONS
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28L SOP 28L PDIP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3
FUNCTIONAL BLOCK DIAGRAM
128 x512
Rev. 1.0
2
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
PIN DESCRIPTIONS
Name
A0 - A12
Type
Input
Function
Address inputs for selecting one of the 8,192 x 8 bit words in the RAM /CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
/CE1,CE2
Input
active when data read from or write to the device. If either chip enable is not active, the device is deselected and in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write operations.
/WE
Input
With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the
/OE
Input
chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive.
DQ0~DQ7 Vcc Gnd NC
I/O Power Power
These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground No connection
TRUTH TABLE
MODE Standby Output Disable Read Write /CE1 H X L L L CE2 X L H H H /WE X X H H L /OE X X H L X DQ0~7 High Z High Z DOUT DIN Vcc Current ICCSB, ICCSB1 ICC ICC ICC
Rev. 1.0
3
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rating
-0.5 to Vcc+0.5 -40 to +125 -65 to +150 1.0 50
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM TBIAS TSTG PT IOUT
Parameter
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Unit
V
O O
C C
W mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial Industrial
Ambient Temperature
0~70oC -40~85oC
Vcc
4.5 ~ 5.5V 4.5 ~ 5.5V
CAPACITANCE(1)(TA=25,f=1.0MHz)
Symbol
CIN CDQ
Parameter
Input Capacitance Input/Output Capacitance
Conduction
VIN=0V VDI/O=0V
MAX.
8 10
Unit
pF pF
1.This parameter is guaranteed, and not 100% tested.
Rev. 1.0
4
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
( TA = 0 ~70 C, Vcc = 5.0V) )
o o
DC ELECTRICAL CHARACTERISTICS
Name VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1 Parameter
Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current Vcc=5.0V
Test Condition
MIN
-0.5
TYP(1)
MAX
0.8
Unit
V
Vcc=5.0V VCC=MAX, VIN=0 to VCC VCC=MAX, /CE1=VIh, or
2.2 -1
Vcc+0.5 1
V uA
Output Leakage Current
CE2= VIL, or /OE=VIh ,or /WE= VIL VIO=0V to VCC
-1
1
uA
Output Low Voltage Output High Voltage Operating Power Supply Current TTL Standby Supply
VCC=MAX, IOL = 1mA VCC=MIN, IOH = -1mA /CE1=VIL, IDQ=0mA, F=FMAX =1/ tRC /CE1=VIH, IDQ=0mA, /CE1VCC-0.2V, CE2= 0.2V, VINVCC-0.2V or VIN0.2V,
o
0.4 2.4
V V
30
mA
10
mA
CMOS Standby Current
1
10
uA
1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
Rev. 1.0
5
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
( TA = 0 ~70 C, Vcc = 5.0V) )
o o
DATA RETENTION CHARACTERISTICS
Name
VDR
Parameter
VCC for Data Retention
Test Condition
/CE1 VCC-0.2V, VIN VCC-0.2V or VIN0.2V /CE1VCC-0.2V, VIN
MIN TYP(1) MAX
2.0
Unit
V
ICCDR
Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
VCC-0.2V or VIN0.2V Refer to Retention Waveform 0 tRC (2)
0.5
5
uA
TCDR tR 1.TA = 25 C
o
ns ns
2. tRC= .Read Cycle Time
LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE1 Controlled )
VCC
tCDR
VIH
Data Retention Mode VDR > 2.0V
tR
VIH
CE1
CE1 > VCC - 0.2V
Rev. 1.0
6
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
LOW Vcc DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
VCC
tCDR
VIL
Data Retention Mode VDR > 2.0V CE2 < 0.2v
tR
VIL
CE2
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times
Input and Output Timing Reference Level Output Load
KEY TO SWITCHING WAVEFORMS
WAVEFORMS INPUTS OUTPUTS
MUST BE STEADY MUST BE STEADY
Vcc/0V 5ns
0.5Vcc See FIGURE 1A and 1B
MAY CHANGE FROM L TO H
DON'T CARE ANY CHANGE PERMITTED
MAY CHANGE FROM H TO L
WILL BE CHANGE FROM H TO L
WILL BE CHANGE FROM L TO H
CHANGE STATE UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH IMPEDANCE OFF STATE
Rev. 1.0
7
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
AC TEST LOADS AND WAVEFORMS
5V
INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE
5V
3857
OUTPUT 1500 30pF
OUTPUT 1500 5pF
FIGURE 1A
FIGURE 1B
AC ELECTRICAL CHARACTERISTICS ( 0~70Vcc=5V ) < READ CYCLE >
JEDEC Name tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX Symbol tRC tAA tACE tOE tCLZ(5) tOLZ(5) tCHZ(5) tOHZ(5) tOH Description
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Address Change to Out Disable 10 5 0 0 10 35 30
3857
-70
MIN 70 70 70 40 MAX
Unit
ns ns ns ns ns ns ns ns ns
Rev. 1.0
8
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 [1,2,4]
READ CYCLE 2 [1,3,4]
READ CYCLE 3
[1,4]
Rev. 1.0
9
High Speed Super Low Power SRAM
8K-Word By 8 Bit
NOTES:
WS6264
1. /WE is high in read Cycle. 2. Device is continuously selected when /CE1 = VIL and CE2=VIH. 3. Address valid prior to or coincident with /CE1 transition low and /or CE2 transition high. 4. /OE = VIL.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
AC ELECTRICAL CHARACTERISTICS ( 0~70Vcc=5V ) < WRITE CYCLE >
JEDEC Name tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHOX Symbol tWC tCW tAS tAW tWP tWR tWHZ(10) tDW tDH tOHZ(10) tOW(10) Description
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold for Write End Output Disable to Output in High Z End of Write to Output Active 40 0 0 5 30
-70
MIN 70 70 0 70 50 0 35 MAX
Unit
ns ns ns ns ns ns ns ns ns ns ns
Rev. 1.0
10
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
WRITE CYCLE2 (Chip Enable Controlled)
Rev. 1.0
11
High Speed Super Low Power SRAM
8K-Word By 8 Bit
NOTES:
WS6264
1. TAS is measured from the address valid to the beginning of write. 2. The internal write time of the memory is defined by the overlap of /CE1 and CE2 active and /WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of /CE1 or /WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the /CE1 low transition or CE2 high transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state. 6. /OE is continuously low (/OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If /CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of /CE1 going low or CE2 going high to the end of write.
ORDER INFORMATION
WS6264LL X X X XX
LL: Low Low power
Temperature: Blank: 0~70C I: -40~85C
Speed: 70: 70ns
Package: NormalFP: 28L SOP-330mil P: 28L PDIP-600mil
Package Material: -: Normal R: Lead and Halogen Free
Rev. 1.0 12
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
PACKAGE DIMENSIONS
28 pin SOP (330 mil) :
SYMBOL UNIT Min. mm
A
A1
A2
b 0.35 _ 0.50
b1 0.35 _ 0.45
c 0.20 _ 0.32
c1
D
E
E1
e
L
L1
y _ _ 0.1 _ _ 0 _ 10 0 _ 10
2.540 0.102 2.362
Nom. 2.692 0.226 2.489 Max. 2.844 0.350 2.616 Min.
0.20 17.983 8.280 11.506 1.118 0.700 1.520 _ 18.110 8.407 11.811 1.270 0.964 1.720 0.28 18.237 8.534 12.116 1.422 1.228 1.920
0.100 0.004 0.093 0.014 0.014 0.008 0.008 0.708 0.326 0.453 0.044 0.0276 0.0598 _ _ _ _ 0.713 0.331 0.465 0.050 0.0380 0.0677 inch Nom. 0.106 0.009 0.098
Max. 0.112 0.014 0.103 0.020 0.018 0.012 0.011 0.718 0.336 0.477 0.056 0.0484 0.0756 0.004
28 pin PDIP (600mil):
SYM BOL UNIT M in. mm
A1
A2 3.683 3.810 3.937 0.145 0.150 0.155
B 0.330 0.457 0.584 0.013 0.018 0.023
B1 1.270 1.524 1.778 0.050 0.060 0.070
c
D
E
E1
e
eB
L
S 1.778 2.032 2.286 0.070 0.080 0.090
Q1 1.651 1.778 1.905 0.065 0.070 0.075 3 6 9 3 6 9
0.254 _ Nom. _ M ax. 0.010 _ Nom. _ M ax. M in.
0.152 36.957 14.986 13.716
2.540 0.254 37.084 15.240 13.818 (TYP) 16.256 3.302 16.764 3.556 0.356 37.211 15.494 13.920 0.006 0.010 0.014 1.455 1.460 1.465 0.590 0.600 0.610 0.540 0.544 0.548 0.620 0.100 (TYP) 0.640 0.660 0.120 0.130 0.140
15.748 3.048
inch
Rev. 1.0
13

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